The present invention is directed to a method of testing a semiconductor device including asynchronous modules, and to a semiconductor device including asynchronous modules.
Different modules in a semiconductor device may be sufficiently asynchronous that the response of the device to test signals is indeterministic, that is to say that the timing of the responses of the asynchronous modules of similar devices produced in different production batches, or of a given device operating at different supply voltages or at different temperatures may differ by one or more clock cycles unpredictably. Semiconductor devices often include more than one clock domain at different frequencies. The different clock domains may have asynchronous clock signal generators, causing the different modules to be asynchronous, for example.
A semiconductor device may also include both a single data rate (‘SDR’) module and a double data rate (‘DDR’) module. An SDR module performs one data transfer per full cycle (rise and fall) of a clock signal, which requires that the clock signal change twice per data transfer. A DDR module transfers data on both the rising and falling edges of the clock signal and, by using both edges of the clock signal, for a given clock frequency a DDR module operates at double the data transfer rate of an SDR module.
Automatic test equipment (‘ATE’) is widely used to test semiconductor devices. When used to test a semiconductor device including asynchronous modules, there is a risk of indeterministic response of the device under test (‘DUT’) if the test operation is carried out at the full clock frequencies and data rates of the DUT, leading to faulty test results and reduced yield in production. If the operation of the modules can be made synchronous during the test, by running the DUT at a single clock frequency for example, the risk of indeterministic response of the DUT may be eliminated. However, the test conditions may no longer be representative of the normal operational data transfer rates of the DUT and the test may not reveal defects, or may signal defects erroneously, because of frequency-dependent parasitic effects and because the modules are operating under test at a different clock frequency from their normal operational clock frequencies, for example.